Experienced EE
Richard Bennett
601 Coast Range Drive, Scotts Valley, CA 95066
(home)------------ (cell)------------ ------------
Qualifications Profile
Analytical and skilled Electrical Engineering Manager with solid and progressive testing and product design career combined with expertise in product engineering and coordination, microcontroller design and oscillator processes, as well as ADC, DAC and other analog circuitry.
• Strong analytical, technical and engineering expertise, and ability to identify and develop new technologies / testing processes of commercial value.
• Adept at handling multiple responsibilities; consistently serve as go-to person to get the job done. Experienced in dealing with overseas contract manufacturers.
• Results-oriented project management, leadership, and communication talents; capable of leading and directing teams to complete projects within rigid time and budget requirements.
Professional Experience
Synaptics Corporation, Synaptics, CA
Test Engineering Manager, 2016 - present
Brought up testing solution for new fingerprint identification chip, designing hardware and software for volume mass production on Teradyne J750, meeting production ramps and maintaining production yields through mass production. Program was used to bring up several follow-on products.
Supervised subsequent program releases.
Hired new and replacement personnel.
Used RADAR tool to automate data collection from compressed STDF tester files, generate Cpk measurements, and view histograms.
Worked with bench and validation engineers and developed system to rapidly deploy new tests, including correlation.
Worked with contract manufacturers to build hardware and implement flash memory testing.
Interfaced with design engineers to implement new design-for-test (DFT) features to speed up test releases and improve coverage.
Senior Test Engineer, 2009 - 2016
Develop and implement test programs for production test and characterization of touch and industry-first combination touch and LCD chip. Bringup of new LCD test platform, including software and hardware design.
Wrote and implemented new tests to leverage the instrumentation of the LCD tester to assist in touch testing, including new calibration techniques to reduce test time.
Implemented new version control system to facilitate testing remote design center.
Wrote new test classes for Advantest T637x LCD test platform, including binning and datalogging routines.
Designed PCB hardware for wafer sort and final test operations.
Actel Corporation, Mountain View, CA
Senior Test Engineer, 2006 - 2008
Develop and implement test programs for production test and characterization of FPGAs. Design, order and debug production hardware. Plan and implement improvements to test procedures including test time reductions and focused calibrations. Verification and disposition of lots on hold. Implement root-cause solutions from internal CARs. Support burn-in and read-and-record programs for release of new silicon and new silicon revisions.
Working in a team environment, helped take Actel Fusion line (Flash-based FPGA with on-board analog) from initial to full production release. Implemented test methodologies to support volume ramp at wafer sort and final test.
Cut test time for package test by 50%.
Implemented focused calibration hardware and software to improve analog throughput and yields.
Significantly improved overall performance and reliability of test program and hardware through improved test methodologies and root-cause problem solving.
Implemented Design-For-Test and participating in test methodologies for next-generation Fusion products.
Microchip Technology Inc., Chandler, AZ
Senior Test Engineer, 1999 - 2006
Perform, prepare and process milestone review/testing in the area of IC and hardware design, and production staff. Analyze and configure test plans for microcontrollers with analog modules on Teradyne J750 tester. Conduct extensive test debugging, custom bench setups and Teradyne J750 protocol development. Offer specialist support in all aspects of AC/DC and analog circuitry. Coordinate Failure Analysis activities. Align operations to ensure optimal customer satisfaction. Train and mentor more than 10 employees in all aspects of validation, product line development, Chandler and Thailand testing, and troubleshooting. Monitor probe/final test yields, quality control and lot reject rates to identify and implement cost effective improvements.
• Reviewed, reengineered and managed testing operations, implementing quality assurance standards and upgrading/supporting business processes.
• Significantly improved overall performance, reliability, and functionality; successfully implemented standard methodology to respond to customer requests.
• Served as interim product engineer, continually performing and excellence in areas of expertise. Orchestrated and facilitated release of Baseline PIC products to market.
• Successfully met critical deadlines and made necessary design and configuration modifications as needed to meet customer requests.
Medtronic Microelectronics Center, Tempe, AZ
Senior IC Test Development Engineer, 1998 - 1999
Spearheaded and coordinated IC test design and implementation for memory, mixed-signal and analog devices. Worked with internal and external customers to understand and meet requirements for testing and characterization.
Sustaining Test Engineer, 1996 - 1998
Tested, evaluated, and configured hardware and software programs; supported and facilitated qualification, yield enhancement, and sustaining activities for tests. Dramatically reduced test times by incorporating process improvements. Planned, coordinated, and scheduled feasibility studies, and surveys of proposed complex software tools, to include evaluations; supported and ensured reliability client software and hardware systems.
IC Test Technician, 1992 - 1996
Conducted extensive maintenance and troubleshooting of wafer test and burn-in equipment. Specialized in Schlumberger S-80s, ULTs, Credence STSs, and LTX Synchro HT. Supported production personnel with wafer and package setups.
* * * * *
Excellent prior experience as Nuclear Submarine Electrical Operator for the US Navy.
Education, Credentials, Skills, Association
Bachelor of Science, Electrical Engineering
Arizona State University, Phoenix, Arizona
Associate of Arts in General Studies
Mesa Community College, Mesa, Arizona
Schlumberger S80 ~ Credence STS ~ Megatest GII
LTX Synchro ~ Teradyne IG-XL Programming
Professional Association
IEEE - The Institute of Electrical and Electronic Engineers, Inc
Technical Skills
MS Excel, MS Word, Solaris, PIC programming, Visual Basic, C++
Richard Bennett
601 Coast Range Drive, Scotts Valley, CA 95066
(home)------------ (cell)------------ ------------
Qualifications Profile
Analytical and skilled Electrical Engineering Manager with solid and progressive testing and product design career combined with expertise in product engineering and coordination, microcontroller design and oscillator processes, as well as ADC, DAC and other analog circuitry.
• Strong analytical, technical and engineering expertise, and ability to identify and develop new technologies / testing processes of commercial value.
• Adept at handling multiple responsibilities; consistently serve as go-to person to get the job done. Experienced in dealing with overseas contract manufacturers.
• Results-oriented project management, leadership, and communication talents; capable of leading and directing teams to complete projects within rigid time and budget requirements.
Professional Experience
Synaptics Corporation, Synaptics, CA
Test Engineering Manager, 2016 - present
Brought up testing solution for new fingerprint identification chip, designing hardware and software for volume mass production on Teradyne J750, meeting production ramps and maintaining production yields through mass production. Program was used to bring up several follow-on products.
Supervised subsequent program releases.
Hired new and replacement personnel.
Used RADAR tool to automate data collection from compressed STDF tester files, generate Cpk measurements, and view histograms.
Worked with bench and validation engineers and developed system to rapidly deploy new tests, including correlation.
Worked with contract manufacturers to build hardware and implement flash memory testing.
Interfaced with design engineers to implement new design-for-test (DFT) features to speed up test releases and improve coverage.
Senior Test Engineer, 2009 - 2016
Develop and implement test programs for production test and characterization of touch and industry-first combination touch and LCD chip. Bringup of new LCD test platform, including software and hardware design.
Wrote and implemented new tests to leverage the instrumentation of the LCD tester to assist in touch testing, including new calibration techniques to reduce test time.
Implemented new version control system to facilitate testing remote design center.
Wrote new test classes for Advantest T637x LCD test platform, including binning and datalogging routines.
Designed PCB hardware for wafer sort and final test operations.
Actel Corporation, Mountain View, CA
Senior Test Engineer, 2006 - 2008
Develop and implement test programs for production test and characterization of FPGAs. Design, order and debug production hardware. Plan and implement improvements to test procedures including test time reductions and focused calibrations. Verification and disposition of lots on hold. Implement root-cause solutions from internal CARs. Support burn-in and read-and-record programs for release of new silicon and new silicon revisions.
Working in a team environment, helped take Actel Fusion line (Flash-based FPGA with on-board analog) from initial to full production release. Implemented test methodologies to support volume ramp at wafer sort and final test.
Cut test time for package test by 50%.
Implemented focused calibration hardware and software to improve analog throughput and yields.
Significantly improved overall performance and reliability of test program and hardware through improved test methodologies and root-cause problem solving.
Implemented Design-For-Test and participating in test methodologies for next-generation Fusion products.
Microchip Technology Inc., Chandler, AZ
Senior Test Engineer, 1999 - 2006
Perform, prepare and process milestone review/testing in the area of IC and hardware design, and production staff. Analyze and configure test plans for microcontrollers with analog modules on Teradyne J750 tester. Conduct extensive test debugging, custom bench setups and Teradyne J750 protocol development. Offer specialist support in all aspects of AC/DC and analog circuitry. Coordinate Failure Analysis activities. Align operations to ensure optimal customer satisfaction. Train and mentor more than 10 employees in all aspects of validation, product line development, Chandler and Thailand testing, and troubleshooting. Monitor probe/final test yields, quality control and lot reject rates to identify and implement cost effective improvements.
• Reviewed, reengineered and managed testing operations, implementing quality assurance standards and upgrading/supporting business processes.
• Significantly improved overall performance, reliability, and functionality; successfully implemented standard methodology to respond to customer requests.
• Served as interim product engineer, continually performing and excellence in areas of expertise. Orchestrated and facilitated release of Baseline PIC products to market.
• Successfully met critical deadlines and made necessary design and configuration modifications as needed to meet customer requests.
Medtronic Microelectronics Center, Tempe, AZ
Senior IC Test Development Engineer, 1998 - 1999
Spearheaded and coordinated IC test design and implementation for memory, mixed-signal and analog devices. Worked with internal and external customers to understand and meet requirements for testing and characterization.
Sustaining Test Engineer, 1996 - 1998
Tested, evaluated, and configured hardware and software programs; supported and facilitated qualification, yield enhancement, and sustaining activities for tests. Dramatically reduced test times by incorporating process improvements. Planned, coordinated, and scheduled feasibility studies, and surveys of proposed complex software tools, to include evaluations; supported and ensured reliability client software and hardware systems.
IC Test Technician, 1992 - 1996
Conducted extensive maintenance and troubleshooting of wafer test and burn-in equipment. Specialized in Schlumberger S-80s, ULTs, Credence STSs, and LTX Synchro HT. Supported production personnel with wafer and package setups.
* * * * *
Excellent prior experience as Nuclear Submarine Electrical Operator for the US Navy.
Education, Credentials, Skills, Association
Bachelor of Science, Electrical Engineering
Arizona State University, Phoenix, Arizona
Associate of Arts in General Studies
Mesa Community College, Mesa, Arizona
Schlumberger S80 ~ Credence STS ~ Megatest GII
LTX Synchro ~ Teradyne IG-XL Programming
Professional Association
IEEE - The Institute of Electrical and Electronic Engineers, Inc
Technical Skills
MS Excel, MS Word, Solaris, PIC programming, Visual Basic, C++